Xilinx rtl schematic not updating

Posted by / 05-Dec-2020 16:43

Xilinx recommends Vivado® Design Suite for new design starts with Virtex®-7, Kintex®-7, Artix®-7, and Zynq®-7000.The ISE Design Suite: Embedded Edition includes Xilinx Platform Studio (XPS), Software Development Kit (SDK), large repository of plug and play IP including Micro Blaze™ Soft Processor and peripherals, and a complete RTL to bit stream design flow.

ISE® design suite supports the Spartan®-6, Virtex®-6, and Cool Runner™ devices, as well as their previous generation families.The ISE Design Suite: System Edition builds on top of the Embedded Edition by adding on System Generator for DSP™.System Generator for DSP is the industry's leading high-level tool for designing high-performance DSP systems using Xilinx programmale devices, providing system modeling and automatic code generation from Simulink® and MATLAB® (The Math Works, Inc.) ISE Web PACK delivers a complete, front-to-back design flow providing instant access to the ISE features and functionality at no cost.PS: I'm using verilog code and schematics in my project if that affects anything.Except as stated herein, none of the Design may be copied, reproduced, distributed, republished, downloaded, displayed, posted, or transmitted in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise, without the prior written consent of Xilinx.

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I'm working on a project using Xilinx ISE on my PC and it's version 14.x When I try to open the project at the university computers which have Xilinx 12.x installed, I get an error that I can't open projects created using later versions of Xilinx.